Integrated circuits (ICs) use metal lines to connect the various circuit elements together. These lines are called interconnect structures. Because a high density of circuit elements and connections is required, it is necessary to use several levels of metal lines. Each level contains a planar structure of metal lines, with layers of an insulator such as silicon dioxide used to separate the levels from one another.
It is necessary to interconnect the layers to one another, to enable current to flow between the layers. These interconnections are called vias. Vias are located in small holes formed in the insulator, and are commonly 0.1 μm in diameter or larger. These holes are filled with a metal to form an interconnection between metal lines in different layers. Such interconnections must be continuous from a lower level of metal to a higher level. If an interconnection is not continuous, the via will be “open”. This defect may cause failure of the integrated circuit.
Open vias can result from a number of process problems. For example, the process of filling the small holes with metal may not fully fill a hole. A residue from a previous process step may impede connection, or the residue may be corrosive and etch away a connection that was properly formed. Such a problem might result in an open via. Also, the formation of subsequent layers of metal requires thermal process steps that may cause a properly formed via connection to “pull back”, leaving a partial connection.
Note that the word “defect” or “failure” is here used to mean not only an open via (discussed above) but also a via connection with greater resistance than a perfectly-formed via (i.e. a fully conductive via). For instance, a perfectly-formed via may have a resistance of 1 ohm, and a partially conductive via may have a higher resistance of 2 ohms (i.e. the resistance is two or more times larger for a defective via than for a perfectly-formed via).
In addition, the formation of a patterned layer of metal on top of another layer requires registration of the lithographic pattern. If the pattern is misaligned, vias from one layer may not land or only partially land onto an underlying metal line, resulting in an “unlanded” or “partially landed” via, which forms a fully open electrical connection, or only a partial electrical connection.
A number of methods of testing vias are available. One method of reliably testing interconnections is electrical testing. For example, a via chain is fabricated and probed for continuity. A via chain is a set of short line segments of conductive material alternating between two layers, connected with vias.
FIG. 1A shows such a via chain 100 as a multi-level interconnect structure formed in a wafer with two layers 113 and 114 formed over a substrate 110. The wafer may have transistors and other devices fabricated within it. Various line segments 131a to 131f and 132a to 132n in chain 100 may be made of a metal such as copper, and are embedded within interlayer dielectric layers 111 and 112. Vias 133a to 133l are shown that interconnect the various line segments in layers 113 and 114 to one another. Vias 133a–133l may have a height (separation distance between layer 113 and 114) on the order of 0.2 to 1.0 μm. Metal line segments (also called simply “lines” or “traces”) 131a to 131f in layer 114 may be 5 μm long and 0.25 μm wide. Metal line segments 132a to 132n in layer 113 are also of the same dimensions in this example. These line segments are connected to form a chain, by vias 133a to 133l. 
Various types of defects can form in vias 133a–133l. For example, small voids can form therein, reducing the cross-section of the via and increasing the resistance. The via hole can be over- or under-etched, causing a change in its size and thereby decreasing or increasing the resistance. A common problem is a failure at the landing site—the point of contact of the via to the underlying line, labeled as site 106 for via 133a contacting to line layer 114. This failure arises, for example, from etch residues left as a result of the formation of the via hole in layer 112. The failure can also arise from thermal stress during the formation of additional metal line and insulator layers above layer 113. The failure is often not an open connection, but a connection of increased resistance. This is a site of potential future failure, since the increased resistance can cause heating when current flows through the via during operation of the integrated circuit.
A significant property of a completed via is its resistance. The frequency distribution of resistance of completed vias is shown in graph 150 of FIG. 1B as line 151. The frequency distribution has a mean value 155. It drops to zero for values of resistance 153 and below, value 153 representing the “over-etched via” described above. In a well-controlled process, an ideal via would have a resistance at value 155. Distribution 151 has a one standard deviation width 152. Values beyond resistance 154 are considered open or failed vias. For an integrated circuit with 5×10^7 vias, this resistance must be greater than the mean value 155 plus six times the standard deviation 152 to ensure a failure rate of less than 10% of the integrated circuits due to bad vias (one in 5'10^8 vias is bad).
A problem in determining the quality of vias is that prior art measurement methods are only able to distinguish completely open vias (vias with no connection whatsoever, some of which may still have too high a resistance to be considered good from the standpoint of circuit function). Consequently, it is necessary to measure a large number of vias to find a small number of bad ones. The conductivity of a chain of vias 133a–133l can be measured by use of probes 140a and 140b (FIG. 1A) that contact chain 100 at the ends of the via chain. To measure the continuity of the chain, an electric current is passed there-through and measured. This method allows a single measurement to determine the continuity of a large number of vias in the chain.
However, such probing has a number of drawbacks when used during manufacturing. First, the just-described “contact” method requires a large area in a production wafer to hold a via chain that is otherwise not a part of a circuit being manufactured. Second, the contact method requires probes to make a contact with chain 100 which may be undesirable during fabrication, since any contact can generate particles and contamination. Third, the contact method cannot be used if a dielectric layer covers the metal lines in layer 113 because the probes need to be in electrical contact with the two ends of the chain 100. Finally, the contact method provides only a single measurement value corresponding to the average via resistance, and cannot isolate individual vias or evaluate a small number of vias in the via chain (unless more complex matrix structures are built that require a large additional area for pads (large metal squares) where the probes contact the structure. Such use of wafer area is undesirable in manufacturing, since the area is not available for product.).
Other methods of examining vias in a wafer relate to various applications of scanning electron microscopes (SEMs). One of these methods is called voltage contrast. Suppose, for example, that vias 133b and 133c are both open. Metal line 132b will then be electrically floating. Under SEM scanning, this segment 132b will charge with electrons and therefore stand out in an SEM image. The limitation of voltage contrast is that it cannot be used with partially failed vias, since any via continuity in a partially failed via will discharge the charge from the segment.
Also, this method cannot be used once a dielectric layer (not shown in FIG. 1) is formed over the segment, since the dielectric will charge up. Therefore, voltage contrast is only usable when the top layer is a metal layer, and cannot evaluate via problems induced by the process of formation of subsequent layers. Moreover, such a prior art measurement is typically used to detect via defects with a resistance above 10 megohms. There is a resistance range from below 10 ohms to over 10 megohms where a via failure is hard to detect. This is also called a “soft failure”.
Another SEM method is sectioning. A sample wafer is broken, or a focused ion beam is used to cut away material, exposing a side view of the via. The SEM can then image the via. This method has limitations of being destructive and slow, and is therefore limited to post-analysis of failures.
Another method was disclosed by Smith et al. in U.S. Pat. No. 5,228,776 that is incorporated herein by reference as background. In this patent, a modulated laser beam creates a thermal wave in a metal line. Specifically, Smith et al. state “By this arrangement, the pump beam can be focused on a metal line in one layer while the probe beam is focused on a line in a different layer. Using this approach, it can be relatively easy to find a flaw in a via which is used to connect the two lines.” Smith et al. also state that “ . . . the assignee's Thermaprobe Imager device is a non-contact technique. However, identification of defective vias has been hampered because the surfaces associated with defective vias are often not optically flat. More particularly, the surfaces can be dimpled, angles, rough or otherwise geometrically distorted and therefore tend to scatter light making reflected power measurements difficult.” Smith et al. further state “First, both the pump and probe beams can be focused on optically flat surfaces even if there are intermediate geometrically distorted surfaces associated with a defect.”
Smith et al.'s method suffers from two drawbacks. First, thermal waves can reflect from interfaces, such as the end of a line, a bend in a line, or a via connection. Such reflections can perturb measurements based on thermal waves that are described by Smith et al. Second, Smith et al. require that the two laser beams must be independently focused at different sites, which can require complicated optical positioning that varies with circuit geometry.
Vias that are only partially conductive can also be found as described in U.S. patent application Ser. No. 10/090,287 that is incorporated by reference above. As described therein, heat is applied to a conductive structure that includes one or more vias, and the temperature of the conductive structure is measured. Then the measured temperature is checked to identify an irregularity (e.g. by comparison with a predetermined limit, or by finding aperiodicity in a scan of a periodic structure). If an irregularity is found in the structure, the wafer is rejected and if there is no irregularity, the wafer is further processed in the wafer fabrication process.
The just-described patent application describes a method of making a number of measurements along the length of a structure, to obtain a sequence of measurements indicative of properties of structure along the length. The measured signal changes with distance, wherein the signal variation depends on the conductivity of various elements (such as vias and traces) that form the structure. Specifically, if vias are arranged periodically in space with a fixed pitch separating two adjacent vias, then the intensity of a signal measured therefrom is periodic as illustrated by FIG. 5 of U.S. patent application Ser. No. 10/090,287. A Fourier transform of the measured signal shows a sharp peak at the spatial frequency, wherein the spatial frequency is inversely related to the pitch of the vias in the structure.
However, when applying the above-described method in an industrial environment, inventors of the current application note that the method is slow because it requires closely spaced measurements on via chains. This is because periodicity (in case of a structure that has vias located at regular spatial intervals, i.e. a fixed pitch) must be noticeable from the measured signal (as a function of distance along the length of the structure). The step size is typically small, on the order of a fraction of the beam diameter (typically <0.5 μm step size). If larger steps are taken, it is uncertain that the beam's spot will be exactly aligned relative to the periodic structure, with the result that an error in alignment causes large swings in the measured signal due to difference in spatial periodicity between the structure and the measurement locations (rather than due to a change in via resistance).